In context: Chip-on-wafer-on-substrate is a packaging expertise that integrates a number of chips right into a single bundle to create high-performance computing and AI parts. The sphere is at the moment dominated by TSMC, although different Taiwanese corporations corresponding to UMC, ASE Expertise Holding, and Powertech Expertise are additionally coming into the market.
With AI exhibiting no indicators of slowing, TSMC can be ramping up its superior chip packaging capabilities over the subsequent few years. Throughout its current earnings name on October 17, the chipmaker revealed that its manufacturing capability for CoWoS packaging expertise is ready to double year-over-year in each 2024 and 2025.
Nonetheless, demand is so sturdy that even with this fast enlargement, the corporate suggests it nonetheless cannot produce packages quick sufficient for its prospects.
At present, superior packaging accounts for under about seven to 9 % of TSMC’s complete income, however it’s a fast-growing phase that’s anticipated to outpace the corporate’s general progress over the subsequent 5 years. Whereas gross margins are barely decrease than TSMC’s common, they’re steadily enhancing as manufacturing quantity will increase.
Initially, the trade rumor mill anticipated TSMC’s CoWoS capability enlargement to start out leveling off by 2026. Early projections had the corporate’s month-to-month packaging quantity topping out round 100,000 to 120,000 wafers that yr. However, shock – AI’s demand retains rising.
With main AI gamers relentlessly driving demand for cutting-edge chips with superior packaging, TSMC has returned to its tools suppliers to plan for even larger CoWoS capability in 2026, in accordance with the report.
These suppliers probably embody corporations like GPTC and Scientech, key suppliers of moist course of tools, corresponding to automated moist benches and single wafer spin processors, which TSMC depends on. Scientech, specifically, seems to have a powerful grip on CoWoS tools orders for the time being.
These suppliers may quickly be printing money because the report suggests TSMC may attain an astonishing 140,000 to 150,000 packaged wafers per 30 days by 2026.
To place that in perspective, by the tip of this yr, the corporate expects its CoWoS capability to achieve round 35,000 to 40,000 wafers per 30 days. In 2025, that determine is predicted to surge to roughly 80,000 wafers.
Past ramping up manufacturing, the chipmaker reportedly plans to modify from standard spherical wafers to rectangular substrates to extend the variety of chips that may be positioned on every wafer.
